1. Field of the Invention
The present invention relates to an oscillation circuit, for example, such as crystal oscillation circuit having a tolerant input circuit to lower the input signal level to a lower level than the transistor rated voltage.
This is a counterpart of Japanese patent application Serial Number 136032/2006, filed on May 16, 2006, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
Conventionally, there is a technology disclosed in the following document as a technology to operate crystal oscillation circuit at low (power supply) voltage.
Patent Document Japanese Patent Laid-Open Number 2004-015314
Some of the low-(power supply)voltage-operating crystal oscillation circuits being disclosed in the above patent document 1 include tolerant input circuits having a function of limit resistance on the input side of the first-stage driver within the crystal oscillation circuit against the case where external clock signal swinging to higher voltage than the above low voltage of crystal oscillation circuit. A MOS transistor (for example, N-cannel type MOS transistor, hereinafter referred to as “NMOS”) having the source electrode connected to the external clock terminal side, the drain electrode connected to the input side of the first-stage driver, and the gate electrode inputted the given voltage can be taken as an example of the above tolerant input circuit.
When an external clock signal having bigger amplitude than the is inputted to the above crystal oscillation circuit, the circuit thereof changes the external clock signal to a clock signal having smaller amplitude than the rated voltage of the low-voltage transistor consisting the first-stage driver by the on-state resistance (hereinafter referred to as “on-resistance”) of the NMOS of the input tolerant circuit, and then the above clock signal is driven by the first-stage driver and outputted from the clock output terminal as the clock signal.